Lost ASIC

Here’s some archived design documents for a failed HP project I worked on. The IP protection should have long expired and technology so outdated that it’s not worth looking.

 

Test Items:

1. VDAC0
2. SAR adc
3. Analog audio AD/DA
4. Digital audio AD/DA

 

Test Steps:

 

Step 1a: Connect SAR and VDAC0

1. • Set adc_mux0 to 4’b0100 on ASIC (SAR receive dac0)
   • Set adc_mux1 to 4’b1000 on ASIC (dac0 output to audio_ad_in)

 

Step 1b: Write to VDAC0 and read from SAR

1. • Write test values to ASIC
   • Calculate expected result on ARM9
   • DM310 read SAR adc result from ASIC

 

Step 1c: Reconnect SAR and VDAC0

1. • Set adc_mux0 to 4’b0000 on ASIC (SAR receive dac output)
   • Set adc_mux1 to (Value incorrect for now)

 

Step 2a: Init DA

1. • Create sine wave on DM310
   • Set mcbsp registers on DM310

 

Step 2b: DA record data

1. • Set audio mode on asic to DA mode
   • Send signal to FPGA to start recording data from SAR adc on ASIC

 

Step 2c: Calculate Frequency

1. • Multiply chunks of the result by Blackman’s window
   • Send chunks through FFT
   • Detect highest and second highest values

 

Step 2d: Output DA result through UART

 

 

 

Step 3a: Init AD

1. • Set ASIC audio mode to AD mode
   • Set FPGA to send sinewave in rom.
   • Set DM310 mcbsp to start receive information

 

Step 3b: Store data

1. • DM310 infinite while loop to store mcbsp buff data into SDRAM

 

Step 3c: Calculate frequency

1. • Stop FPGA from sending data
   • Multiply chunks of the result by Blackman’s window
   • Send chunks through FFT
   • Detect highest and second highest values

 

Step 3d: Output AD result through UART

 

Step 4a: Turn off asic

1. • Set audio mode to 0 on asic
   • Turn off gated clock
   • Reset audio

 

Step 4b: Turn off FPGA

1. • Clear FPGA SDRAM for audio
   • Return FPGA to normal mode

 

Step 4c: Output result